The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method for making semiconductor device having a memory cell. Merely by way of example, the invention has been applied to layer-by-layer silicon growth through atomic-layer deposition (ALD) epitaxy for making a device with thin film transistor (TFT) memory cell structure. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to making silicon-on-insulator (SOI) layer, silicon channel layer, and thin silicon charge trapping layers for a variety of devices including dynamic random access memory devices, static random access memory devices, flash memory devices, three-dimensional memory arrays, and others.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of iCs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of iCs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed.
Over the past, reducing memory devices have been a challenging task. As an example, for non-volatile memory devices the high density memory development is hindered by the inability to scale down the memory cell size without reducing the memory capacitance per unit area. In the past, various conventional techniques have been developed for memory cell structures with reduced dimensions. Unfortunately, these conventional techniques have often been inadequate.
From the above, it is seen that an improved technique for processing semiconductor devices, particularly those including the three-dimensional (3D) memory cell structure, is desired.